Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs

Kiichi Tachi*, Sylvain Barraud, Kuniyuki Kakushima, Hiroshi Iwai, Sorin Cristoloveanu, Thomas Ernst

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

Low-temperature electrical characteristics of n-type gate-all-around vertically-stacked silicon nanowire (SNW) field-effect transistors (FETs) with high-k/metal gate have been investigated and are compared to those with Fin and fully-depleted silicon-on-insulator (FD SOI) FETs. In particular, the effective electron mobilities behaviors are discussed. Nanowires with a rectangular cross section of 15 nm in width and 19 nm in height have shown a strongly degraded mobility as compared to those with Fin and FD SOI FETs. Low-temperature measurements have revealed that the mobility degradation is due to higher surface-roughness limited mobility. On the other hand, no significant difference in the interface trap densities among the kinds of FETs measured in the study have been observed from the temperature dependence in the subthreshold slope.

Original languageEnglish
Pages (from-to)885-888
Number of pages4
JournalMicroelectronics Reliability
Volume51
Issue number5
DOIs
StatePublished - May 2011

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