Comparison of electrical characteristics of N-type silicon junctionless transistors with and without film profile engineering by TCAD simulation

Jung Ruey Tsai, Horng-Chih Lin, Hsiu Fu Chang, Bo Shiuan Shie, Ting Ting Wen, Tiao Yuan Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Field-effect transistors (FETs) with junctionless (JL) channels have recently attracted much attention for various applications, such as metal-oxide semiconductor thin-film transistors (TFTs) [1], memory devices [2] and Si nanowire TFTs [3, 4]. The Si junctionless (JL) transistors employing high dopant concentration (> 1019 cm3) in the source, drain, and nano-scaled channel have been demonstrated to provide excellent electrical characteristics. More recently, film profile engineering (FPE) concept for fabricating downscaled ZnO and IGZO TFTs [5, 6] have been proposed to obtain high-on/off current ratio and great subthreshold swing. Nevertheless, it emphasizes a significant issue of source/drain (S/D) series resistance on the downscaled device performance that needs to be further verified. In this work, electrical performance of downscaled N-type Si JL TFTs with FPE channel and conventional ones will be compared with each other by Sentaurus technology computer aided design (TCAD) simulation [7].

Original languageEnglish
Title of host publication2015 Silicon Nanoelectronics Workshop, SNW 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863485389
StatePublished - 24 Sep 2015
EventSilicon Nanoelectronics Workshop, SNW 2015 - Kyoto, Japan
Duration: 14 Jun 201515 Jun 2015

Publication series

Name2015 Silicon Nanoelectronics Workshop, SNW 2015

Conference

ConferenceSilicon Nanoelectronics Workshop, SNW 2015
CountryJapan
CityKyoto
Period14/06/1515/06/15

Keywords

  • Doping
  • Logic gates
  • Performance evaluation
  • Resistance
  • Silicon
  • Thin film transistors

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