Compact on-chip ECC for low cost flash memories

Toru Tanzawa*, Tomoharu Tanaka, Ken Takeuchi, Shirota Riichiro, Seiichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, Kazunori Ohuchi

*Corresponding author for this work

Research output: Contribution to conferencePaper

2 Scopus citations

Abstract

A compact on-chip ECC for low cost Flash memories has been developed to minimize the chip size increase. The proposed on-chip ECC implemented on a 64M NAND Flash memory has suppressed the chip size penalty to 1.9%. Moreover, the cumulative sector error rate can be improved by 4 orders after 106 write/erase cycles.

Original languageEnglish
Pages74-75
Number of pages2
DOIs
StatePublished - 1 Jan 1996
EventProceedings of the 1996 Symposium on VLSI Circuits - Honolulu, HI, USA
Duration: 13 Jun 199615 Jun 1996

Conference

ConferenceProceedings of the 1996 Symposium on VLSI Circuits
CityHonolulu, HI, USA
Period13/06/9615/06/96

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  • Cite this

    Tanzawa, T., Tanaka, T., Takeuchi, K., Riichiro, S., Aritome, S., Watanabe, H., Hemink, G., Shimizu, K., Sato, S., Takeuchi, Y., & Ohuchi, K. (1996). Compact on-chip ECC for low cost flash memories. 74-75. Paper presented at Proceedings of the 1996 Symposium on VLSI Circuits, Honolulu, HI, USA, . https://doi.org/10.1109/VLSIC.1996.507722