A compact on-chip ECC for low cost Flash memories has been developed to minimize the chip size increase. The proposed on-chip ECC implemented on a 64M NAND Flash memory has suppressed the chip size penalty to 1.9%. Moreover, the cumulative sector error rate can be improved by 4 orders after 106 write/erase cycles.
|Number of pages||2|
|State||Published - 1 Jan 1996|
|Event||Proceedings of the 1996 Symposium on VLSI Circuits - Honolulu, HI, USA|
Duration: 13 Jun 1996 → 15 Jun 1996
|Conference||Proceedings of the 1996 Symposium on VLSI Circuits|
|City||Honolulu, HI, USA|
|Period||13/06/96 → 15/06/96|