Compact modeling for new transistor structures

Chen-Ming Hu, M. Dunga, C. H. Lin, D. Lu, A. Niknejad

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

Using embedded SRAM as a path, FinFET may enter manufacturing at 32nm. FinFET provides several advantages over the planar MOSFET structure-smaller size, larger current, smaller leakage, and less variation in threshold voltage. A compact model of multi-gate transistors will facilitate their adoption. BSIM-MG is a surface-potential based compact model of multi-gate MOSFETs fabricated on either SOI or bulk substrates. The effects of body doping are modeled. It can also model a double-gate transistor with independently biased front and back gates and asymmetric front and back gate work-functions and dielectric thicknesses.

Original languageEnglish
Pages285-288
Number of pages4
DOIs
StatePublished - 1 Jan 2007
Event12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007 - Vienna, Austria
Duration: 25 Sep 200727 Sep 2007

Conference

Conference12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007
CountryAustria
CityVienna
Period25/09/0727/09/07

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