This paper presents a compact IDCT processor for HDTV applications by using cyclic convolution and hardwired multipliers. By properly arranging the input sequence, we formulate IDCT into cyclic convolution that is regular and suitable for VLSI implementation. The hardwired multipliers that implement multiplications with scaled IDCT coefficients are optimized by common subexpression techniques. Based on these techniques, our proposed design costs 7504 gates plus 1024 bits of memory with 100 Mpixels/sec throughput.
|Number of pages||8|
|Journal||IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation|
|State||Published - 1 Dec 1999|
|Event||1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation' - Taipei, Taiwan|
Duration: 20 Oct 1999 → 22 Oct 1999