Compact IDCT processor for HDTV applications

Tian-Sheuan Chang*, Jiun-In  Guo, Chein Wei Jen

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations


This paper presents a compact IDCT processor for HDTV applications by using cyclic convolution and hardwired multipliers. By properly arranging the input sequence, we formulate IDCT into cyclic convolution that is regular and suitable for VLSI implementation. The hardwired multipliers that implement multiplications with scaled IDCT coefficients are optimized by common subexpression techniques. Based on these techniques, our proposed design costs 7504 gates plus 1024 bits of memory with 100 Mpixels/sec throughput.

Original languageEnglish
Pages (from-to)151-158
Number of pages8
JournalIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
StatePublished - 1 Dec 1999
Event1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation' - Taipei, Taiwan
Duration: 20 Oct 199922 Oct 1999

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