Communication synthesis for interconnect minimization targeting distributed register-file microarchitecture

Juinn-Dar Huang, Chia I. Chen*, Yen Ting Lin, Wan Ling Hsu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


In deep-submicron era, wire delay is becoming a bottleneck while pursuing even higher system clock speed. Several distributed register (DR) architectures have been proposed to cope with this problem by keeping most wires local. In this article, we propose a new resourceconstrained communication synthesis algorithm for optimizing both interisland connections (IICs) and latency targeting on distributed registerfile microarchitecture (DRFM). The experimental results show that up to 24.7% and 12.7% reduction on IIC and latency can be achieved respectively as compared to the previous work.

Original languageEnglish
Pages (from-to)1151-1155
Number of pages5
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number4
StatePublished - 1 Jan 2011


  • Communication synthesis
  • Distributed register-file microarchitecture
  • Interconnect minimization
  • Resource binding
  • Scheduling

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