Communication synthesis for interconnect minimization in multicycle communication architecture

Ya Shih Huang, Yu Ju Hong, Juinn-Dar Huang

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


In deep-submicron technology, several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle communication. In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global interconnect resource minimization. We also present an innovative algorithm with regard of both spatial and temporal perspectives. It features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works.

Original languageEnglish
Pages (from-to)3143-3150
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number12
StatePublished - 1 Jan 2009


  • Communication synthesis
  • Interconnect minimization
  • Multicycle communication
  • Resource allocation
  • Resource sharing
  • Routing
  • Scheduling

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