Common-centroid FinFET placement considering the impact of gate misalignment

Po Hsun Wu, Po-Hung Lin, X. Li, Tsung Yi Ho

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

The FinFET technology has been regarded as a better alternative among different device technologies at 22nm node and beyond due to more effective channel control and lower power consumption. However, the gate misalignment problem resulting from process variation based on the FinFET technology becomes even severer compared with the conventional planar CMOS technology. Such misalignment may increase the threshold voltage and decrease the drain current of a single transistor. When applying the FinFET technology to analog circuit design, the variation of drain currents will destroy the current matching among transistors and degrade the circuit performance. In this paper, we present the first FinFET placement technique for analog circuits considering the impact of gate misalignment together with systematic and random mismatch. Experimental results show that the proposed algorithms can obtain an optimized common-centroid FinFET placement with much better current matching.

Original languageEnglish
Title of host publicationISPD 2015 - Proceedings of the ACM International Symposium on Physical Design 2015
PublisherAssociation for Computing Machinery
Pages25-31
Number of pages7
ISBN (Electronic)9781450333993
DOIs
StatePublished - 29 Mar 2015
Event18th ACM International Symposium on Physical Design, ISPD 2015 - Monterey, United States
Duration: 29 Mar 20151 Apr 2015

Publication series

NameProceedings of the International Symposium on Physical Design
Volume29-March-2015

Conference

Conference18th ACM International Symposium on Physical Design, ISPD 2015
CountryUnited States
CityMonterey
Period29/03/151/04/15

Keywords

  • Analog placement
  • Common centroid
  • FinFET
  • Gate misalignment

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