Collaborative voltage scaling with online STA and variable-latency datapath

Tay Jyi Lin*, Pi Cheng Hsiao, Chi Hung Lin, Shu Chang Kuo, Chou Kun Lin, Yu Ting Kuo, Chih-Wei Liu, Yuan Hua Chu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper presents an event-driven adaptive voltage scaling (AVS) system, where a vanguard collaborates with a rearguard to find a minimal supply voltage. While the vanguard is responsible for the slack cycle time estimation, the rearguard allows voltage over-scaling with a variable-latency datapath. An improved vanguard is proposed based on online static timing analysis (STA), which monitors a scalable number of critical path candidates at run time. In our simulations, the delay estimation error is within 10%, which is relatively small compared to critical path variations of prevailing multi-Vt designs in deep-submicron era. A testchip with a 32-bit tiny RISC has been fabricated with the TSMC 65nm LP process technology to demonstrate the effectiveness.

Original languageEnglish
Title of host publicationGLSVLSI'10 - Proceedings of the Great Lakes Symposium on VLSI 2010
Pages347-352
Number of pages6
DOIs
StatePublished - 16 Jul 2010
Event20th Great Lakes Symposium on VLSI, GLSVLSI 2010 - Providence, RI, United States
Duration: 16 May 201018 May 2010

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference20th Great Lakes Symposium on VLSI, GLSVLSI 2010
CountryUnited States
CityProvidence, RI
Period16/05/1018/05/10

Keywords

  • adaptive voltage scaling
  • collaborative voltage scaling
  • online STA
  • variable-latency datapath

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