Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is questionable whether we can successfully introduce sub-10 nm CMOS LSIs into market or not. In this paper, limitation and its possible causes for the downscaling of CMOS are discussed from many aspects.
|Number of pages||4|
|Journal||Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS|
|State||Published - 2004|
|Event||5th IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS - , Dominican Republic|
Duration: 3 Nov 2004 → 5 Nov 2004