CMOS technology future

Hiroshi Iwai*

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

Abstract

Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is questionable whether we can successfully introduce sub-10 nm CMOS LSIs into market or not. In this paper, limitation and its possible causes for the downscaling of CMOS are discussed from many aspects.

Original languageEnglish
Pages (from-to)179-182
Number of pages4
JournalProceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS
StatePublished - 2004
Event5th IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS - , Dominican Republic
Duration: 3 Nov 20045 Nov 2004

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