CMOS technology for MS/RF SoC

Carlos H. Diaz*, Denny D. Tang, Jack Yuan Chen Sun

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

51 Scopus citations


Accelerated scaling of CMOS technology has contributed to remove otherwise fundamental barriers preempting its widespread application to mixed-signal/radio-frequency (MS/RF) segments. Improvements in device speed, matching, and minimum noise figure are all consistent with fundamental scaling trends. Other figures-of-merit such as linearity and 1/f noise do not scale favorably but are not considered to be roadblocks when viewed from a circuit design perspective. Furthermore, interconnect architectural scaling trends in logic technology have facilitated improvements in passive-component performance metrics. These improvements compounded with innovations in circuit design have made CMOS technology the primary choice for cost driven MS/RF applications. This paper reviews active and passive elements of CMOS MS/RF system-on-chip (SoC) technology from scaling perspective. The paper also discusses the implications that physical phenomena such as mechanical stress and gate leakage as well as gate patterning have on technology definition and characterization.

Original languageEnglish
Pages (from-to)557-566
Number of pages10
JournalIEEE Transactions on Electron Devices
Issue number3
StatePublished - Mar 2003


  • (MS/RF)
  • 1/f noise
  • Analog
  • Analog CMOS
  • CMOS system-on-chip (SoC)
  • CMOS technology
  • Device isolation
  • Gate dielectric
  • Gate dielectric direct tunneling
  • Gate patterning
  • Integrated capacitors
  • Integrated inductors
  • Integrated resistors
  • Line-edge roughness (LER)
  • Matching
  • Mechanical stress in MOS devices
  • Mixed-signal (MS)
  • Mixed-signal/radio-frequency
  • Noise isolation
  • Passive elements
  • Source-drain engineering
  • System-on-chip (SoC)

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