CMOS technology after reaching the scale limit

Hiroshi Iwai*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

17 Scopus citations

Abstract

Progress of CMOS LSI has been accomplished by the downsizing of MOSFETs. However, it has been expected that the downscaling will reach its limits about the gate length of 5 nm around the year of 2020. 2020 is not too far, but there is no sufficiently clear image for the world after CMOS reaches its scaling limit. This paper will discuss the picture of the CMOS technology in the world after the 2020.

Original languageEnglish
Title of host publicationIWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology
Pages1-2
Number of pages2
DOIs
StatePublished - 2008
EventIWJT-2008 - International Workshop on Junction Technology - Shanghai, China
Duration: 15 May 200816 May 2008

Publication series

NameIWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology

Conference

ConferenceIWJT-2008 - International Workshop on Junction Technology
CountryChina
CityShanghai
Period15/05/0816/05/08

Cite this