CMOS LSIs are expected to continue to progress well into the next century. The progress has been driven by the downsizing of the components in an LSI, such as MOSFETs. However, even before the downsizing of MOSFETs reaches its fundamental limit, the downsizing is expected to encounter severe technological and economic problems at the beginning of next century when the minimum feature size of LSIs is going to shift to 0.1 and sub-0.1 μm. In this paper, CMOS scaling towards its limits are explained based on the experimental results of the downsizing MOSFET into such dimension, and further concept for deep-sub-0.1 μm CMOS is described.
|Number of pages||4|
|State||Published - 1998|
|Event||Proceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology - Beijing, China|
Duration: 21 Oct 1998 → 23 Oct 1998
|Conference||Proceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology|
|Period||21/10/98 → 23/10/98|