CMOS scaling towards its limits

Hiroshi Iwai*

*Corresponding author for this work

Research output: Contribution to conferencePaper

7 Scopus citations

Abstract

CMOS LSIs are expected to continue to progress well into the next century. The progress has been driven by the downsizing of the components in an LSI, such as MOSFETs. However, even before the downsizing of MOSFETs reaches its fundamental limit, the downsizing is expected to encounter severe technological and economic problems at the beginning of next century when the minimum feature size of LSIs is going to shift to 0.1 and sub-0.1 μm. In this paper, CMOS scaling towards its limits are explained based on the experimental results of the downsizing MOSFET into such dimension, and further concept for deep-sub-0.1 μm CMOS is described.

Original languageEnglish
Pages31-34
Number of pages4
StatePublished - 1998
EventProceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology - Beijing, China
Duration: 21 Oct 199823 Oct 1998

Conference

ConferenceProceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology
CityBeijing, China
Period21/10/9823/10/98

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