CMOS scaling in the 0.1-μm, 1.X-volt regime for high-performance applications

G. G. Shahidi*, J. D. Warnock, J. Comfort, S. Fischer, P. A. McFarland, A. Acovic, T. I. Chappell, B. A. Chappell, T. H. Ning, C. J. Anderson, R. H. Dennard, J. Y.C. Sun, M. R. Polcari, B. Davari

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

28 Scopus citations

Abstract

Deep-submicron CMOS is the primary technology for ULSI systems. Currently, the state-of-the-art CMOS device has a 0.25-μm effective channel length and operates at 2.5 V. As the CMOS technology is extended into the deep submicron range, it is estimated that the next generation will have a nominal channel length of 0.15 μm with a supply voltage of ≤2 V. In this paper, two potential technologies with application to 1.X-V CMOS are presented. First, a bulk CMOS technology with the nominal channel length of 0.15 μm is described. It is next argued that because of issues related to power dissipation, such a device may face problems when operated at its maximum speed-density potential in high-performance logic chips. CMOS on a silicon-on-insulator (SOI) substrate offers circuits with lower power at the same performance. Such a CMOS technology, with channel lengths down to less than 0.1 μm, is described next. This technology is particularly useful for applications near a 1.0-V supply. We describe, for example, a 512Kb SRAM with an access time of less than 3.5 ns at 1.X V. The clear power-performance advantage of CMOS on SOI over that of CMOS on bulk silicon in the 1.X-V regime makes it the technology of choice for sub-0.25-μm CMOS generations.

Original languageEnglish
Pages (from-to)229-244
Number of pages16
JournalIBM Journal of Research and Development
Volume39
Issue number1-2
DOIs
StatePublished - 1995

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