Recently, CMOS downsizing has been accelerated very aggressively in both production and reseach level, and even transistor operation of a 6 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into market or not. In this paper, limitation and its possible causes for the downscaling of CMOS towards sub-10 nm are discussed with consideration of past CMOS predictions for the limitation.
|Number of pages||6|
|Journal||Proceedings of the IEEE International Conference on VLSI Design|
|State||Published - 2004|
|Event||Proceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design - Mumbai, India|
Duration: 5 Jan 2004 → 9 Jan 2004