CMOS scaling for sub-90 nm to sub-10 nm

Hiroshi Iwai*

*Corresponding author for this work

Research output: Contribution to journalConference article

13 Scopus citations

Abstract

Recently, CMOS downsizing has been accelerated very aggressively in both production and reseach level, and even transistor operation of a 6 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into market or not. In this paper, limitation and its possible causes for the downscaling of CMOS towards sub-10 nm are discussed with consideration of past CMOS predictions for the limitation.

Original languageEnglish
Pages (from-to)30-35
Number of pages6
JournalProceedings of the IEEE International Conference on VLSI Design
Volume17
StatePublished - 2004
EventProceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design - Mumbai, India
Duration: 5 Jan 20049 Jan 2004

Fingerprint Dive into the research topics of 'CMOS scaling for sub-90 nm to sub-10 nm'. Together they form a unique fingerprint.

  • Cite this