CMOS prescaler(s) with maximum 208-GHz dividing speed and 37-GHz time-interleaved dual-injection locking range

Qun Jane Gu*, Heng Yu Jian, Zhiwei Xu, Yi Cheng Wu, Mau-Chung Chang, Yves Baeyens, Young Kai Chen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

10 Scopus citations

Abstract

To enable CMOS prescaler(s) for submillimeter-wave radio-frequency synthesis, we present a new dynamic frequency divider topology according to a time-interleaved dual-injection locking scheme. Consequently, the prototype prescalers implemented with 65-nm CMOS technology have demonstrated ultrahigh operation speeds up to 208 GHz, with ultrawide locking range up to 37 GHz, with 2.5-mW power consumption. The achieved performance figure of merit (FOM) [i.e., (speed × range)/power in GHz2/mW] is roughly an order of magnitude higher than that of the state of the art.

Original languageEnglish
Article number5934371
Pages (from-to)393-397
Number of pages5
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume58
Issue number7
DOIs
StatePublished - 1 Jul 2011

Keywords

  • CMOS prescaler
  • injection locking frequency divider
  • submillimeter wave circuits
  • wide locking range

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