CMOS prescaler(s) with maximum 208-GHz dividing speed and 37-GHz time-interleaved dual-injection locking range

Qun Jane Gu; Heng Yu Jian; Zhiwei Xu; Yi Cheng Wu; Mau-Chung Chang; Yves Baeyens; Young Kai Chen

doi:10.1109/TCSII.2011.2158267

CMOS prescaler(s) with maximum 208-GHz dividing speed and 37-GHz time-interleaved dual-injection locking range

Qun Jane Gu^*, Heng Yu Jian, Zhiwei Xu, Yi Cheng Wu, Mau-Chung Chang, Yves Baeyens, Young Kai Chen

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

To enable CMOS prescaler(s) for submillimeter-wave radio-frequency synthesis, we present a new dynamic frequency divider topology according to a time-interleaved dual-injection locking scheme. Consequently, the prototype prescalers implemented with 65-nm CMOS technology have demonstrated ultrahigh operation speeds up to 208 GHz, with ultrawide locking range up to 37 GHz, with 2.5-mW power consumption. The achieved performance figure of merit (FOM) [i.e., (speed × range)/power in GHz²/mW] is roughly an order of magnitude higher than that of the state of the art.

Original language	English
Article number	5934371
Pages (from-to)	393-397
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	58
Issue number	7
DOIs	https://doi.org/10.1109/TCSII.2011.2158267
State	Published - 1 Jul 2011

Keywords

CMOS prescaler
injection locking frequency divider
submillimeter wave circuits
wide locking range

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title = "CMOS prescaler(s) with maximum 208-GHz dividing speed and 37-GHz time-interleaved dual-injection locking range",

abstract = "To enable CMOS prescaler(s) for submillimeter-wave radio-frequency synthesis, we present a new dynamic frequency divider topology according to a time-interleaved dual-injection locking scheme. Consequently, the prototype prescalers implemented with 65-nm CMOS technology have demonstrated ultrahigh operation speeds up to 208 GHz, with ultrawide locking range up to 37 GHz, with 2.5-mW power consumption. The achieved performance figure of merit (FOM) [i.e., (speed × range)/power in GHz2/mW] is roughly an order of magnitude higher than that of the state of the art.",

keywords = "CMOS prescaler, injection locking frequency divider, submillimeter wave circuits, wide locking range",

author = "Gu, {Qun Jane} and Jian, {Heng Yu} and Zhiwei Xu and Wu, {Yi Cheng} and Mau-Chung Chang and Yves Baeyens and Chen, {Young Kai}",

year = "2011",

month = jul,

day = "1",

doi = "10.1109/TCSII.2011.2158267",

language = "English",

volume = "58",

pages = "393--397",

journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",

issn = "1549-8328",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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CMOS prescaler(s) with maximum 208-GHz dividing speed and 37-GHz time-interleaved dual-injection locking range. / Gu, Qun Jane; Jian, Heng Yu; Xu, Zhiwei; Wu, Yi Cheng; Chang, Mau-Chung; Baeyens, Yves; Chen, Young Kai.

In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 58, No. 7, 5934371, 01.07.2011, p. 393-397.

Research output: Contribution to journal › Article › peer-review

TY - JOUR

T1 - CMOS prescaler(s) with maximum 208-GHz dividing speed and 37-GHz time-interleaved dual-injection locking range

AU - Gu, Qun Jane

AU - Jian, Heng Yu

AU - Xu, Zhiwei

AU - Wu, Yi Cheng

AU - Chang, Mau-Chung

AU - Baeyens, Yves

AU - Chen, Young Kai

PY - 2011/7/1

Y1 - 2011/7/1

N2 - To enable CMOS prescaler(s) for submillimeter-wave radio-frequency synthesis, we present a new dynamic frequency divider topology according to a time-interleaved dual-injection locking scheme. Consequently, the prototype prescalers implemented with 65-nm CMOS technology have demonstrated ultrahigh operation speeds up to 208 GHz, with ultrawide locking range up to 37 GHz, with 2.5-mW power consumption. The achieved performance figure of merit (FOM) [i.e., (speed × range)/power in GHz2/mW] is roughly an order of magnitude higher than that of the state of the art.

AB - To enable CMOS prescaler(s) for submillimeter-wave radio-frequency synthesis, we present a new dynamic frequency divider topology according to a time-interleaved dual-injection locking scheme. Consequently, the prototype prescalers implemented with 65-nm CMOS technology have demonstrated ultrahigh operation speeds up to 208 GHz, with ultrawide locking range up to 37 GHz, with 2.5-mW power consumption. The achieved performance figure of merit (FOM) [i.e., (speed × range)/power in GHz2/mW] is roughly an order of magnitude higher than that of the state of the art.

KW - CMOS prescaler

KW - injection locking frequency divider

KW - submillimeter wave circuits

KW - wide locking range

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JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

SN - 1549-8328

IS - 7

M1 - 5934371

ER -

CMOS prescaler(s) with maximum 208-GHz dividing speed and 37-GHz time-interleaved dual-injection locking range

Abstract

Keywords

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