CMOS-on-SOI ESD protection networks

S. Voldman*, R. Schulz, J. Howard, V. Gross, S. Wu, A. Yapsir, D. Sadana, H. Hovel, J. Walker, F. Assaderaghi, B. Chen, J. Y.C. Sun, G. Shahidi

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


ESD robustness of 4 kV HBM is achieved in CMOS-on-SOI ESD protection networks in an advanced sub-0.25 μm mainstream CMOS-on-SOI technology. Design layout, body contact, floating-gate effects and novel ESD protection implementations are discussed.

Original languageEnglish
Pages (from-to)333-350
Number of pages18
JournalJournal of Electrostatics
Issue number4
StatePublished - Jan 1998


  • CMOS
  • ESD
  • Protection
  • SOI technology

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