CMOS-on-SOI ESD protection networks

S. Voldman*, R. Schulz, J. Howard, V. Gross, S. Wu, A. Yapsir, D. Sadana, H. Hovel, J. Walker, F. Assaderaghi, B. Chen, J. Y.C. Sun, G. Shahidi

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

26 Scopus citations


ESD robustness of 4 kV HBM is achieved in CMOS-on-SOI ESD protection networks in an advanced sub-0.25 μm CMOS-on-SOI technology. Design layout, body contact, floating gate effects and novel ESD protection implementations are discussed.

Original languageEnglish
Pages (from-to)291-301
Number of pages11
JournalElectrical Overstress/Electrostatic Discharge Symposium Proceedings
StatePublished - 1996
EventProceedings of the 1996 Electrical Overstress/Electrostatic Discharge Symposium - Orlando, FL, USA
Duration: 10 Sep 199612 Sep 1996

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