CMOS on-chip ESD protection design with substrate-triggering technique

Ming-Dou Ker*, Tung Yang Chen, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

To increase the ESD robustness and to reduce the trigger voltage of the ESD protection devices, a substrate-triggering technique is proposed to effectively enhance the ESD-protection efficiency of CMOS on-chip ESD protection circuits in submicron CMOS technologies. With suitable substrate bias, the ESD protection devices can sustain much higher ESD-stress voltage within small layout area. Two practical design examples of the input ESD protection circuit and the VDD-to-VSS ESD clamp circuit are designed by using the substrate-triggering technique to verify the ESD protection efficiency.

Original languageEnglish
Pages273-276
Number of pages4
DOIs
StatePublished - 1 Dec 1998
EventProceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology - Lisboa, Portugal
Duration: 7 Sep 199810 Sep 1998

Conference

ConferenceProceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology
CityLisboa, Portugal
Period7/09/9810/09/98

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