CMOS logic device and circuit performance of Si gate all around nanowire MOSFET

Kaushik Nayak, Mohit Bajaj, Aniruddha Konar, Philip J. Oldiges, Kenji Natori, Hiroshi Iwai, Kota V.R.M. Murali, Valipe Ramgopal Rao

Research output: Contribution to journalArticle

43 Scopus citations

Abstract

In this paper, a detailed 3-D numerical analysis is carried out to study and evaluate CMOS logic device and circuit performance of gate-all-around (GAA) Si nanowire (NW) field-effect transistors (FETs) operating in sub-22-nm CMOS technologies. Employing a coupled drift-diffusion room temperature carrier transport formulation, with 2-D quantum confinement effects, we numerically simulate Si GAA NWFET electrical characteristics. The simulation predictions, on the device performance, short channel effects, and their dependence on NW geometry scaling, are in good agreement with the Si NWFET experimental data reported in literature. Superior electrostatic integrity, OFF-state device performance, lower circuit delays, and faster switching in the Si GAA NWFET-based CMOS circuits are numerically demonstrated in comparison with an Si-on-insulator FinFET. The mixed-mode numerical simulations also predict low supply voltage operations for the Si NWFET-based logic circuits.

Original languageEnglish
Article number6862016
Pages (from-to)3066-3074
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume61
Issue number9
DOIs
StatePublished - Sep 2014

Keywords

  • Circuit delays
  • CMOS
  • device performance
  • electrostatic integrity
  • gate-all-around (GAA)
  • logic circuits
  • mixed-mode (MM) simulations
  • quantum confinement (QC)
  • silicon nanowire (NW) field-effect transistor (FET)

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