CMOS downsizing and high-K gate insulator technology

H. Iwai, S. Ohmi

Research output: Contribution to conferencePaperpeer-review

Abstract

Downscaling of MOSFETs is the driving force of the development of new generation CMOS ULSIs. Now, gate lengths of the transistors have reached sub-100 nm in production and 15 nm in research. However, many difficulties are expected to further downsizing of the device dimensions. The biggest difficulty at this moment is the thinning of the gate oxide. In this paper, problems the downsizing and expected solutions in particular those for the gate oxide thinning for miniaturized CMOS ULSI devices are explained.

Original languageEnglish
DOIs
StatePublished - 2002
Event4th IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS 2002 - Oranjestad, Aruba, Netherlands
Duration: 17 Apr 200219 Apr 2002

Conference

Conference4th IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS 2002
CountryNetherlands
CityOranjestad, Aruba
Period17/04/0219/04/02

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