CMOS downsizing and high-K gate insulator technology

H. Iwai; S. Ohmi

doi:10.1109/ICCDCS.2002.1004072

CMOS downsizing and high-K gate insulator technology

H. Iwai, S. Ohmi

International College of Semiconductor Technology

Research output: Contribution to conference › Paper › peer-review

Abstract

Downscaling of MOSFETs is the driving force of the development of new generation CMOS ULSIs. Now, gate lengths of the transistors have reached sub-100 nm in production and 15 nm in research. However, many difficulties are expected to further downsizing of the device dimensions. The biggest difficulty at this moment is the thinning of the gate oxide. In this paper, problems the downsizing and expected solutions in particular those for the gate oxide thinning for miniaturized CMOS ULSI devices are explained.

Original language	English
DOIs	https://doi.org/10.1109/ICCDCS.2002.1004072
State	Published - 2002
Event	4th IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS 2002 - Oranjestad, Aruba, Netherlands Duration: 17 Apr 2002 → 19 Apr 2002

Conference

Conference	4th IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS 2002
Country	Netherlands
City	Oranjestad, Aruba
Period	17/04/02 → 19/04/02

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abstract = "Downscaling of MOSFETs is the driving force of the development of new generation CMOS ULSIs. Now, gate lengths of the transistors have reached sub-100 nm in production and 15 nm in research. However, many difficulties are expected to further downsizing of the device dimensions. The biggest difficulty at this moment is the thinning of the gate oxide. In this paper, problems the downsizing and expected solutions in particular those for the gate oxide thinning for miniaturized CMOS ULSI devices are explained.",

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AB - Downscaling of MOSFETs is the driving force of the development of new generation CMOS ULSIs. Now, gate lengths of the transistors have reached sub-100 nm in production and 15 nm in research. However, many difficulties are expected to further downsizing of the device dimensions. The biggest difficulty at this moment is the thinning of the gate oxide. In this paper, problems the downsizing and expected solutions in particular those for the gate oxide thinning for miniaturized CMOS ULSI devices are explained.

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Y2 - 17 April 2002 through 19 April 2002

ER -

CMOS downsizing and high-K gate insulator technology

Abstract

Conference

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