CMOS downscaling and process induced damages

H. Iwai

doi:10.1109/PPID.2003.1199718

CMOS downscaling and process induced damages

H. Iwai^*

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The progress of electronic circuits has been made by the downsizing of its components such as MOSFETs. Recently, CMOS downsizing has been accelerated very aggressively, and even transistor operation of a 6 nm gate length p-channel MOSFET has been reported. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into the market or not. In this paper, past and expected future trends of CMOS downscaling are described including the issue of process-induced damage.

Original language	English
Title of host publication	2003 8th International Symposium on Plasma- and Process-Induced Damage, P2ID 2003
Editors	Koji Eriguchi, S. Krishnan, Terence Hook
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-11
Number of pages	11
ISBN (Electronic)	0780377478
DOIs	https://doi.org/10.1109/PPID.2003.1199718
State	Published - 2003
Event	2003 8th International Symposium on Plasma- and Process-Induced Damage, P2ID 2003 - Corbeil-Essonnes, France Duration: 24 Apr 2003 → 25 Apr 2003

Publication series

Name	International Symposium on Plasma Process-Induced Damage, P2ID, Proceedings
Volume	2003-January

Conference

Conference	2003 8th International Symposium on Plasma- and Process-Induced Damage, P2ID 2003
Country	France
City	Corbeil-Essonnes
Period	24/04/03 → 25/04/03

Access to Document

10.1109/PPID.2003.1199718

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Iwai, H. (2003). CMOS downscaling and process induced damages. In K. Eriguchi, S. Krishnan, & T. Hook (Eds.), 2003 8th International Symposium on Plasma- and Process-Induced Damage, P2ID 2003 (pp. 1-11). [1199718] (International Symposium on Plasma Process-Induced Damage, P2ID, Proceedings; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PPID.2003.1199718

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abstract = "The progress of electronic circuits has been made by the downsizing of its components such as MOSFETs. Recently, CMOS downsizing has been accelerated very aggressively, and even transistor operation of a 6 nm gate length p-channel MOSFET has been reported. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into the market or not. In this paper, past and expected future trends of CMOS downscaling are described including the issue of process-induced damage.",

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Iwai, H 2003, CMOS downscaling and process induced damages. in K Eriguchi, S Krishnan & T Hook (eds), 2003 8th International Symposium on Plasma- and Process-Induced Damage, P2ID 2003., 1199718, International Symposium on Plasma Process-Induced Damage, P2ID, Proceedings, vol. 2003-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-11, 2003 8th International Symposium on Plasma- and Process-Induced Damage, P2ID 2003, Corbeil-Essonnes, France, 24/04/03. https://doi.org/10.1109/PPID.2003.1199718

CMOS downscaling and process induced damages. / Iwai, H.

2003 8th International Symposium on Plasma- and Process-Induced Damage, P2ID 2003. ed. / Koji Eriguchi; S. Krishnan; Terence Hook. Institute of Electrical and Electronics Engineers Inc., 2003. p. 1-11 1199718 (International Symposium on Plasma Process-Induced Damage, P2ID, Proceedings; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - The progress of electronic circuits has been made by the downsizing of its components such as MOSFETs. Recently, CMOS downsizing has been accelerated very aggressively, and even transistor operation of a 6 nm gate length p-channel MOSFET has been reported. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into the market or not. In this paper, past and expected future trends of CMOS downscaling are described including the issue of process-induced damage.

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Iwai H. CMOS downscaling and process induced damages. In Eriguchi K, Krishnan S, Hook T, editors, 2003 8th International Symposium on Plasma- and Process-Induced Damage, P2ID 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 1-11. 1199718. (International Symposium on Plasma Process-Induced Damage, P2ID, Proceedings). https://doi.org/10.1109/PPID.2003.1199718