CMOS downscaling and process induced damages

H. Iwai*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The progress of electronic circuits has been made by the downsizing of its components such as MOSFETs. Recently, CMOS downsizing has been accelerated very aggressively, and even transistor operation of a 6 nm gate length p-channel MOSFET has been reported. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into the market or not. In this paper, past and expected future trends of CMOS downscaling are described including the issue of process-induced damage.

Original languageEnglish
Title of host publication2003 8th International Symposium on Plasma- and Process-Induced Damage, P2ID 2003
EditorsKoji Eriguchi, S. Krishnan, Terence Hook
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-11
Number of pages11
ISBN (Electronic)0780377478
DOIs
StatePublished - 2003
Event2003 8th International Symposium on Plasma- and Process-Induced Damage, P2ID 2003 - Corbeil-Essonnes, France
Duration: 24 Apr 200325 Apr 2003

Publication series

NameInternational Symposium on Plasma Process-Induced Damage, P2ID, Proceedings
Volume2003-January

Conference

Conference2003 8th International Symposium on Plasma- and Process-Induced Damage, P2ID 2003
CountryFrance
CityCorbeil-Essonnes
Period24/04/0325/04/03

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  • Cite this

    Iwai, H. (2003). CMOS downscaling and process induced damages. In K. Eriguchi, S. Krishnan, & T. Hook (Eds.), 2003 8th International Symposium on Plasma- and Process-Induced Damage, P2ID 2003 (pp. 1-11). [1199718] (International Symposium on Plasma Process-Induced Damage, P2ID, Proceedings; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PPID.2003.1199718