CMOS device architecture and technology for the 0.25 micron to 0.025 micron generations

Hiroshi Iwai*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

Device structures and technologies for high-speed logic CMOS LSIs have been reviewed, covering the range from several microns to the far future of 1/40 micron devices. The future 0.25 to 0.1 pm generation was investigated in detail. In this generation, optimum design of the impurity profile and fine control over impurity doping - to suppress short-channel effects and to minimize the series source/drain resistance will be die critical issues. New doping techniques will need to be developed to meet the requirements. Intelligent CAD systems which are able to create an optimum interconnect design for high-speed operation will become indispensable, as will highly reliable circuits. For the sub-tenth micron range, undoped epitaxial channel MOSFETs and double-gate SOI MOSFETs appear to be most promising, and correct operation of these devices was confirmed through simulations. However, no concept of a realistic ULSI based on these transistors is available at this point.

Original languageEnglish
Title of host publicationESSDERC 1993 - Proceedings of the 23rd European Solid State Device Research Conference
EditorsJ. P. Noblanc, P. Gentil, M. Verdone, J. Borel, A. Nouailhat
PublisherIEEE Computer Society
Pages513-520
Number of pages8
ISBN (Electronic)2863321358
ISBN (Print)9782863321355
StatePublished - 1993
Event23rd European Solid State Device Research Conference, ESSDERC 1993 - Grenoble, France
Duration: 13 Sep 199316 Sep 1993

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Conference

Conference23rd European Solid State Device Research Conference, ESSDERC 1993
CountryFrance
CityGrenoble
Period13/09/9316/09/93

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