CMOS current-mode implementation of spatiotemporal probabilistic neural networks for speech recognition

Chung-Yu Wu*, Ron Yi Liu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

In this paper, a Spatiotemporal Probabilistic Neural Network (SPNN) is proposed for spatiotemporal pattern recognition. This new model is developed by applying the concept of Gaussian density function to the network structure of the SPR (Spatiotemporal Pattern Recognition). The main advantages of this model include faster training and recalling process for patterns. In addition, the overall architecture is also simple, modular, regular, locally connected, and suitable for VLSI implementation. One set of independent speaker isolated (Mandarin digit) speech database is used as an example to demonstrate the superiority of the neural networks for spatiotemporal pattern recognition. The testing result with a reduced error rate of 7% shows that the SPNN is very attractive and effective for practical applications. p ]The CMOS current-mode IC technology is used to implement the SPNN to achieve the objective of minimum classification error in a more direct manner. In this design, neural computation is performed in analog circuits while template information is stored in digital circuits. The prototyping speech recognition processor for the 12th LPC calculation is designed by 1.2 μm CMOS technology. The HSPICE simulation results are also presented, which verifies the function of the designed neural system.

Original languageEnglish
Pages (from-to)67-84
Number of pages18
JournalJournal of VLSI Signal Processing
Volume10
Issue number1
DOIs
StatePublished - 1 Jun 1995

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