Clock tree aware post-global placement optimization

Hong Yan Su, Po Ting Chiang, Radhamanjari Samanta, Yih-Lang Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Power consumption is one of the key optimization objectives for modern integrated circuit designs. More than 40% of the total power consumption is contributed by clock trees due to their high frequency of switching and high capacitance. In the traditional physical design flow, placement is done before clock tree synthesis (CTS). CTS constructs a tree to connect the clock source with all the registers. Therefore, optimization of clock trees is limited by the quality of register placement. This paper proposes a post-global placement optimization procedure that integrates a fast three stage CTS method based on modified k-means clustering technique into a global placer. The fast three stage CTS constructs a virtual clock tree to guide global placement to favor CTS. Then a multi-level clock net contractive force according to the virtual clock tree is inserted to optimize register locations for reducing the clock tree wirelength. The experimental results show that the proposed optimization approach can reduce both the clock tree wirelength and clock net switching power at the cost of slight increase in half perimeter wirelength (HPWL).

Original languageEnglish
Title of host publication2017 2nd International Conference on Integrated Circuits and Microsystems, ICICM 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages86-90
Number of pages5
ISBN (Electronic)9781538635063
DOIs
StatePublished - 29 Dec 2017
Event2nd International Conference on Integrated Circuits and Microsystems, ICICM 2017 - Nanjing, China
Duration: 8 Nov 201711 Nov 2017

Publication series

Name2017 2nd International Conference on Integrated Circuits and Microsystems, ICICM 2017
Volume2017-November

Conference

Conference2nd International Conference on Integrated Circuits and Microsystems, ICICM 2017
CountryChina
CityNanjing
Period8/11/1711/11/17

Keywords

  • Clock tree synthesis (CTS)
  • force-directed
  • post-global placement

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