Clock planning for multi-voltage and multi-mode designs

Chang Cheng Tsai*, Tzu Hen Lin, Shin Han Tsai, Hung-Ming Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Low power demand drives the development of lower power design architectures, among which multiple supply voltage is one of the state-of-the-art techniques to achieve low power. In addition, dynamic voltage frequency scaling and adaptive voltage scaling are popular power saving techniques during chip operation to provide different modes for various performance requirements. It is therefore very challenging to generate a clock tree for different operation modes. This paper proposes several implementations on this important issue, one of which can provide smallest clock latency and minimum clock skew on average of required operation modes in multi-voltage designs.

Original languageEnglish
Title of host publicationProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
Pages654-658
Number of pages5
DOIs
StatePublished - 22 Jun 2011
Event12th International Symposium on Quality Electronic Design, ISQED 2011 - Santa Clara, CA, United States
Duration: 14 Mar 201116 Mar 2011

Publication series

NameProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

Conference

Conference12th International Symposium on Quality Electronic Design, ISQED 2011
CountryUnited States
CitySanta Clara, CA
Period14/03/1116/03/11

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