A computationally efficient submicron MOSFET I-V model for circuit simulation in SPICE is provided. It is an improved model of the MOS LEVEL3 MOS model in SPICE and supports the design of conventional as well as LDD (lightly doped drain) MOSFETs down to the submicron range. The drain-source series resistance and three-dimensional geometry effects are included in the model. In addition, the model allows fast extraction of model parameters which can be linked with SPICE. Accuracy and benchmark tests show substantial improvements over the original LEVEL3 model.
|State||Published - 1 Dec 1989|
|Event||Proceedings of the Second Annual IEEE ASIC Seminar and Exhibit - Rochester, NY, USA|
Duration: 25 Sep 1989 → 28 Sep 1989
|Conference||Proceedings of the Second Annual IEEE ASIC Seminar and Exhibit|
|City||Rochester, NY, USA|
|Period||25/09/89 → 28/09/89|