Circuit simulation model of submicron MOSFETs for SPICE

Steve S. Chung*, T. S. Lin, Y. G. Chen

*Corresponding author for this work

Research output: Contribution to conferencePaper

Abstract

A computationally efficient submicron MOSFET I-V model for circuit simulation in SPICE is provided. It is an improved model of the MOS LEVEL3 MOS model in SPICE and supports the design of conventional as well as LDD (lightly doped drain) MOSFETs down to the submicron range. The drain-source series resistance and three-dimensional geometry effects are included in the model. In addition, the model allows fast extraction of model parameters which can be linked with SPICE. Accuracy and benchmark tests show substantial improvements over the original LEVEL3 model.

Original languageEnglish
StatePublished - 1 Dec 1989
EventProceedings of the Second Annual IEEE ASIC Seminar and Exhibit - Rochester, NY, USA
Duration: 25 Sep 198928 Sep 1989

Conference

ConferenceProceedings of the Second Annual IEEE ASIC Seminar and Exhibit
CityRochester, NY, USA
Period25/09/8928/09/89

Fingerprint Dive into the research topics of 'Circuit simulation model of submicron MOSFETs for SPICE'. Together they form a unique fingerprint.

  • Cite this

    Chung, S. S., Lin, T. S., & Chen, Y. G. (1989). Circuit simulation model of submicron MOSFETs for SPICE. Paper presented at Proceedings of the Second Annual IEEE ASIC Seminar and Exhibit, Rochester, NY, USA, .