Circuit performance variability decomposition

Michael Orshansky; Costas Spanos; Chen-Ming Hu

doi:10.1109/IWSTM.1999.773184

Circuit performance variability decomposition

Michael Orshansky^*, Costas Spanos, Chen-Ming Hu

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Contribution to conference › Paper › peer-review

20 Scopus citations

Abstract

Circuit performance variability composition is analyzed. Traditionally, the device variability has been the dominant source. It is believed that with continuing technology scaling into deep sub-micron regime, interconnect constitutes an increasing portion of the overall circuit delay, and variability. In this paper, we analytically investigate the delay variability composition for an advanced 0.18 μm CMOS technology, accounting for the significant intra-field variability. A more realistic model to estimate the variance of global interconnect lines is proposed. The results indicate that the device variability of good designs contributes about 90% of the overall variability.

Original language	English
Pages	10-13
Number of pages	4
DOIs	https://doi.org/10.1109/IWSTM.1999.773184
State	Published - 1 Dec 1999
Event	Proceedings of the 1999 4th International Workshop on Statistical Metrology (1999 IWSM) - Kyoto, Jpn Duration: 12 Jun 1999 → 12 Jun 1999

Conference

Conference	Proceedings of the 1999 4th International Workshop on Statistical Metrology (1999 IWSM)
City	Kyoto, Jpn
Period	12/06/99 → 12/06/99

Access to Document

10.1109/IWSTM.1999.773184

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title = "Circuit performance variability decomposition",

abstract = "Circuit performance variability composition is analyzed. Traditionally, the device variability has been the dominant source. It is believed that with continuing technology scaling into deep sub-micron regime, interconnect constitutes an increasing portion of the overall circuit delay, and variability. In this paper, we analytically investigate the delay variability composition for an advanced 0.18 μm CMOS technology, accounting for the significant intra-field variability. A more realistic model to estimate the variance of global interconnect lines is proposed. The results indicate that the device variability of good designs contributes about 90% of the overall variability.",

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AB - Circuit performance variability composition is analyzed. Traditionally, the device variability has been the dominant source. It is believed that with continuing technology scaling into deep sub-micron regime, interconnect constitutes an increasing portion of the overall circuit delay, and variability. In this paper, we analytically investigate the delay variability composition for an advanced 0.18 μm CMOS technology, accounting for the significant intra-field variability. A more realistic model to estimate the variance of global interconnect lines is proposed. The results indicate that the device variability of good designs contributes about 90% of the overall variability.

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