Circuit performance variability composition is analyzed. Traditionally, the device variability has been the dominant source. It is believed that with continuing technology scaling into deep sub-micron regime, interconnect constitutes an increasing portion of the overall circuit delay, and variability. In this paper, we analytically investigate the delay variability composition for an advanced 0.18 μm CMOS technology, accounting for the significant intra-field variability. A more realistic model to estimate the variance of global interconnect lines is proposed. The results indicate that the device variability of good designs contributes about 90% of the overall variability.
|Number of pages||4|
|State||Published - 1 Dec 1999|
|Event||Proceedings of the 1999 4th International Workshop on Statistical Metrology (1999 IWSM) - Kyoto, Jpn|
Duration: 12 Jun 1999 → 12 Jun 1999
|Conference||Proceedings of the 1999 4th International Workshop on Statistical Metrology (1999 IWSM)|
|Period||12/06/99 → 12/06/99|