Circuit performance variability decomposition

Michael Orshansky*, Costas Spanos, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

20 Scopus citations

Abstract

Circuit performance variability composition is analyzed. Traditionally, the device variability has been the dominant source. It is believed that with continuing technology scaling into deep sub-micron regime, interconnect constitutes an increasing portion of the overall circuit delay, and variability. In this paper, we analytically investigate the delay variability composition for an advanced 0.18 μm CMOS technology, accounting for the significant intra-field variability. A more realistic model to estimate the variance of global interconnect lines is proposed. The results indicate that the device variability of good designs contributes about 90% of the overall variability.

Original languageEnglish
Pages10-13
Number of pages4
DOIs
StatePublished - 1 Dec 1999
EventProceedings of the 1999 4th International Workshop on Statistical Metrology (1999 IWSM) - Kyoto, Jpn
Duration: 12 Jun 199912 Jun 1999

Conference

ConferenceProceedings of the 1999 4th International Workshop on Statistical Metrology (1999 IWSM)
CityKyoto, Jpn
Period12/06/9912/06/99

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