Circuit performance of double-gate SOI CMOS

C. H. Lin, Pin Su, Y. Taur, X. Xi, I. He, A. M. Niknejad, M. Chan, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

13 Scopus citations


As CMOS technology is fast moving toward the scaling limit, the double-gate (DG) MOSFETs is considered the most promising structure to suppress the short channel effect for a given equivalent gate oxide thickness by using two gates to control the channel [1]. There are two main types of DG MOSFETs: ( 1 ) the symmetric DG (SDG) device with both gates of identical work functions, and (2) the asymmetric'DG (ADG) device with different work functions for the gates. Although the characteristics of SDG and ADG device have been investigated by many groups (2-4), the relative circuit performance of these two devices still remains controversial. In this paper, the performance of DG MOSFETs from the circuit-design perspective is examined via simulation using device structures based on the ITRS specification [ 5 ] . The propagation delay (l,J and energy dissipation of DG CMOS inverter chains with different number of fan-out (FO) are investigated. Load capacitors are added to the output node of each inverter to simulate the parasitic wiring capacitance (C,1ml) between two stages (Fig. 1).

Original languageEnglish
Title of host publication2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)0780381394, 9780780381391
StatePublished - 1 Jan 2003
EventInternational Semiconductor Device Research Symposium, ISDRS 2003 - Washington, United States
Duration: 10 Dec 200312 Dec 2003

Publication series

Name2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings


ConferenceInternational Semiconductor Device Research Symposium, ISDRS 2003
CountryUnited States

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