Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory

T. W. Lin; S. H. Ku; C. H. Cheng; C. W. Lee; Ijen-Huang; Wen Jer Tsai; T. C. Lu; W. P. Lu; K. C. Chen; Ta-Hui Wang; Chih Yuan Lu

doi:10.1109/IRPS.2018.8353679

Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory

T. W. Lin, S. H. Ku, C. H. Cheng, C. W. Lee, Ijen-Huang, Wen Jer Tsai, T. C. Lu, W. P. Lu, K. C. Chen, Ta-Hui Wang, Chih Yuan Lu

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

Vt instability caused by random telegraph noise (RTN) in floating gate flash memories beyond 20nm is studied comprehensively. Experiments reveal that the RTN would cause Vt distribution with a kinked tail which re-distributes to a 'Gaussian-like' shape rapidly and was measured by the self-established Budget Product Tester (BPT). A Multi-Times Verify (MTV) algorithm to mitigate the statistical tail, thus enlarging operation window is also exhibited by BPT. In further, a probability model to portray the compact Vt distribution under MTV is proposed. Finally, the impact of MTV on lowering the requirement of Error-correcting code (ECC) bit is also demonstrated.

Original language	English
Title of host publication	2018 IEEE International Reliability Physics Symposium, IRPS 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	PMY.61-PMY.65
ISBN (Electronic)	9781538654798
DOIs	https://doi.org/10.1109/IRPS.2018.8353679
State	Published - 25 May 2018
Event	2018 IEEE International Reliability Physics Symposium, IRPS 2018 - Burlingame, United States Duration: 11 Mar 2018 → 15 Mar 2018

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
Volume	2018-March
ISSN (Print)	1541-7026

Conference

Conference	2018 IEEE International Reliability Physics Symposium, IRPS 2018
Country	United States
City	Burlingame
Period	11/03/18 → 15/03/18

Access to Document

10.1109/IRPS.2018.8353679

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Lin, T. W., Ku, S. H., Cheng, C. H., Lee, C. W., Ijen-Huang, Tsai, W. J., Lu, T. C., Lu, W. P., Chen, K. C., Wang, T-H., & Lu, C. Y. (2018). Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory. In 2018 IEEE International Reliability Physics Symposium, IRPS 2018 (pp. PMY.61-PMY.65). (IEEE International Reliability Physics Symposium Proceedings; Vol. 2018-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IRPS.2018.8353679

Lin, T. W. ; Ku, S. H. ; Cheng, C. H. ; Lee, C. W. ; Ijen-Huang ; Tsai, Wen Jer ; Lu, T. C. ; Lu, W. P. ; Chen, K. C. ; Wang, Ta-Hui ; Lu, Chih Yuan. / Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory. 2018 IEEE International Reliability Physics Symposium, IRPS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. PMY.61-PMY.65 (IEEE International Reliability Physics Symposium Proceedings).

@inproceedings{283240f1a86e436aaa86a124c0da5876,

title = "Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory",

abstract = "Vt instability caused by random telegraph noise (RTN) in floating gate flash memories beyond 20nm is studied comprehensively. Experiments reveal that the RTN would cause Vt distribution with a kinked tail which re-distributes to a 'Gaussian-like' shape rapidly and was measured by the self-established Budget Product Tester (BPT). A Multi-Times Verify (MTV) algorithm to mitigate the statistical tail, thus enlarging operation window is also exhibited by BPT. In further, a probability model to portray the compact Vt distribution under MTV is proposed. Finally, the impact of MTV on lowering the requirement of Error-correcting code (ECC) bit is also demonstrated.",

author = "Lin, {T. W.} and Ku, {S. H.} and Cheng, {C. H.} and Lee, {C. W.} and Ijen-Huang and Tsai, {Wen Jer} and Lu, {T. C.} and Lu, {W. P.} and Chen, {K. C.} and Ta-Hui Wang and Lu, {Chih Yuan}",

year = "2018",

month = may,

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doi = "10.1109/IRPS.2018.8353679",

language = "English",

series = "IEEE International Reliability Physics Symposium Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "2018 IEEE International Reliability Physics Symposium, IRPS 2018",

note = "null ; Conference date: 11-03-2018 Through 15-03-2018",

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Lin, TW, Ku, SH, Cheng, CH, Lee, CW, Ijen-Huang, Tsai, WJ, Lu, TC, Lu, WP, Chen, KC, Wang, T-H & Lu, CY 2018, Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory. in 2018 IEEE International Reliability Physics Symposium, IRPS 2018. IEEE International Reliability Physics Symposium Proceedings, vol. 2018-March, Institute of Electrical and Electronics Engineers Inc., pp. PMY.61-PMY.65, 2018 IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, United States, 11/03/18. https://doi.org/10.1109/IRPS.2018.8353679

Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory. / Lin, T. W.; Ku, S. H.; Cheng, C. H.; Lee, C. W.; Ijen-Huang; Tsai, Wen Jer; Lu, T. C.; Lu, W. P.; Chen, K. C.; Wang, Ta-Hui; Lu, Chih Yuan.

2018 IEEE International Reliability Physics Symposium, IRPS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. PMY.61-PMY.65 (IEEE International Reliability Physics Symposium Proceedings; Vol. 2018-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory

AU - Lin, T. W.

AU - Ku, S. H.

AU - Cheng, C. H.

AU - Lee, C. W.

AU - Ijen-Huang,

AU - Tsai, Wen Jer

AU - Lu, T. C.

AU - Lu, W. P.

AU - Chen, K. C.

AU - Wang, Ta-Hui

AU - Lu, Chih Yuan

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N2 - Vt instability caused by random telegraph noise (RTN) in floating gate flash memories beyond 20nm is studied comprehensively. Experiments reveal that the RTN would cause Vt distribution with a kinked tail which re-distributes to a 'Gaussian-like' shape rapidly and was measured by the self-established Budget Product Tester (BPT). A Multi-Times Verify (MTV) algorithm to mitigate the statistical tail, thus enlarging operation window is also exhibited by BPT. In further, a probability model to portray the compact Vt distribution under MTV is proposed. Finally, the impact of MTV on lowering the requirement of Error-correcting code (ECC) bit is also demonstrated.

AB - Vt instability caused by random telegraph noise (RTN) in floating gate flash memories beyond 20nm is studied comprehensively. Experiments reveal that the RTN would cause Vt distribution with a kinked tail which re-distributes to a 'Gaussian-like' shape rapidly and was measured by the self-established Budget Product Tester (BPT). A Multi-Times Verify (MTV) algorithm to mitigate the statistical tail, thus enlarging operation window is also exhibited by BPT. In further, a probability model to portray the compact Vt distribution under MTV is proposed. Finally, the impact of MTV on lowering the requirement of Error-correcting code (ECC) bit is also demonstrated.

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Lin TW, Ku SH, Cheng CH, Lee CW, Ijen-Huang, Tsai WJ et al. Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory. In 2018 IEEE International Reliability Physics Symposium, IRPS 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. PMY.61-PMY.65. (IEEE International Reliability Physics Symposium Proceedings). https://doi.org/10.1109/IRPS.2018.8353679