Charge-trapping-induced parasitic capacitance and resistance in SONOS TFTs under gate bias stress

Chia Sheng Lin*, Ying Chung Chen, Ting Chang Chang, Fu Yen Jian, Hung Wei Li, Shih Ching Chen, Ying Shao Chuang, Te Chih Chen, Ya-Hsiang Tai, Ming Hsien Lee, Jim Shone Chen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


This letter investigates the charge-trapping-induced parasitic resistance and capacitance in siliconoxidenitrideoxidesilicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in off-state C-V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.

Original languageEnglish
Article number5680573
Pages (from-to)321-323
Number of pages3
JournalIEEE Electron Device Letters
Issue number3
StatePublished - 1 Mar 2011


  • Capacitancevoltage characteristics
  • semiconductor device reliability
  • SONOS devices

Fingerprint Dive into the research topics of 'Charge-trapping-induced parasitic capacitance and resistance in SONOS TFTs under gate bias stress'. Together they form a unique fingerprint.

Cite this