Charge-trapping-induced parasitic capacitance and resistance in SONOS TFTs under gate bias stress

Chia Sheng Lin; Ying Chung Chen; Ting Chang Chang; Fu Yen Jian; Hung Wei Li; Shih Ching Chen; Ying Shao Chuang; Te Chih Chen; Ya-Hsiang Tai; Ming Hsien Lee; Jim Shone Chen

doi:10.1109/LED.2010.2095819

Charge-trapping-induced parasitic capacitance and resistance in SONOS TFTs under gate bias stress

Chia Sheng Lin^*, Ying Chung Chen, Ting Chang Chang, Fu Yen Jian, Hung Wei Li, Shih Ching Chen, Ying Shao Chuang, Te Chih Chen, Ya-Hsiang Tai, Ming Hsien Lee, Jim Shone Chen

^*Corresponding author for this work

Department of Photonics

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

This letter investigates the charge-trapping-induced parasitic resistance and capacitance in siliconoxidenitrideoxidesilicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in off-state C-V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.

Original language	English
Article number	5680573
Pages (from-to)	321-323
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	32
Issue number	3
DOIs	https://doi.org/10.1109/LED.2010.2095819
State	Published - 1 Mar 2011

Keywords

Capacitancevoltage characteristics
semiconductor device reliability
SONOS devices

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title = "Charge-trapping-induced parasitic capacitance and resistance in SONOS TFTs under gate bias stress",

abstract = "This letter investigates the charge-trapping-induced parasitic resistance and capacitance in siliconoxidenitrideoxidesilicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in off-state C-V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.",

keywords = "Capacitancevoltage characteristics, semiconductor device reliability, SONOS devices",

author = "Lin, {Chia Sheng} and Chen, {Ying Chung} and Chang, {Ting Chang} and Jian, {Fu Yen} and Li, {Hung Wei} and Chen, {Shih Ching} and Chuang, {Ying Shao} and Chen, {Te Chih} and Ya-Hsiang Tai and Lee, {Ming Hsien} and Chen, {Jim Shone}",

year = "2011",

month = mar,

day = "1",

doi = "10.1109/LED.2010.2095819",

language = "English",

volume = "32",

pages = "321--323",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

Charge-trapping-induced parasitic capacitance and resistance in SONOS TFTs under gate bias stress. / Lin, Chia Sheng; Chen, Ying Chung; Chang, Ting Chang; Jian, Fu Yen; Li, Hung Wei; Chen, Shih Ching; Chuang, Ying Shao; Chen, Te Chih; Tai, Ya-Hsiang; Lee, Ming Hsien; Chen, Jim Shone.

In: IEEE Electron Device Letters, Vol. 32, No. 3, 5680573, 01.03.2011, p. 321-323.

Research output: Contribution to journal › Article › peer-review

TY - JOUR

T1 - Charge-trapping-induced parasitic capacitance and resistance in SONOS TFTs under gate bias stress

AU - Lin, Chia Sheng

AU - Chen, Ying Chung

AU - Chang, Ting Chang

AU - Jian, Fu Yen

AU - Li, Hung Wei

AU - Chen, Shih Ching

AU - Chuang, Ying Shao

AU - Chen, Te Chih

AU - Tai, Ya-Hsiang

AU - Lee, Ming Hsien

AU - Chen, Jim Shone

PY - 2011/3/1

Y1 - 2011/3/1

N2 - This letter investigates the charge-trapping-induced parasitic resistance and capacitance in siliconoxidenitrideoxidesilicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in off-state C-V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.

AB - This letter investigates the charge-trapping-induced parasitic resistance and capacitance in siliconoxidenitrideoxidesilicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in off-state C-V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.

KW - Capacitancevoltage characteristics

KW - semiconductor device reliability

KW - SONOS devices

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U2 - 10.1109/LED.2010.2095819

DO - 10.1109/LED.2010.2095819

M3 - Article

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VL - 32

SP - 321

EP - 323

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 3

M1 - 5680573

ER -

Charge-trapping-induced parasitic capacitance and resistance in SONOS TFTs under gate bias stress

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Keywords

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