Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure

Ya-Chi Cheng, Hung Bin Chen, Jun-Ji Su, Chi-Shen Shao, Cheng-Ping Wang, Chun-Yen Chang, Yung-Chun Wu

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (> 1 mu A/mu m). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I-on/I-off current ratio is over 10(8) A/A for L-g = 1 mu m. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V-th in multi-V-th circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.
Original languageEnglish
Article number669
JournalNanoscale Research Letters
Issue number9
DOIs
StatePublished - 11 Dec 2014

Keywords

  • Junctionless (JL); Thin-film transistor (TFT); Raised source-and-drain (raised S/D); Dual-gate; Reliability
  • SILICON

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