TY - JOUR
T1 - Characterization ofglobal inversion layer in thin-gate-oxide deep-submicron p-MOSFETS
AU - Yu, Bin
AU - Imai, Kiyotaga
AU - Hu, Chen-Ming
PY - 1998/3/30
Y1 - 1998/3/30
N2 - A simple electrical method is presented for the characterization of the inversion layer in p-channel MOSFET's with either p+ poly gate (surface-channel, SC) or n+ poly gate (buried-channel, BC). The dc centroid of the inversion layer profile, Xc, represents the effective thickness of the inversion layer in the SC device or the physical location of the buried-channel in the BC device. For the first time, it is well demonstrated that, based on the small-signal gate-to-channel capacitance measurement, the global inversion layer hole profiles in both types of p-MOSFET's can be constructed from three elements, i.e., Xc (dc centroid), Xw (band diagram characteristic width) and ΔNinv (increment of net carrier area density).
AB - A simple electrical method is presented for the characterization of the inversion layer in p-channel MOSFET's with either p+ poly gate (surface-channel, SC) or n+ poly gate (buried-channel, BC). The dc centroid of the inversion layer profile, Xc, represents the effective thickness of the inversion layer in the SC device or the physical location of the buried-channel in the BC device. For the first time, it is well demonstrated that, based on the small-signal gate-to-channel capacitance measurement, the global inversion layer hole profiles in both types of p-MOSFET's can be constructed from three elements, i.e., Xc (dc centroid), Xw (band diagram characteristic width) and ΔNinv (increment of net carrier area density).
UR - http://www.scopus.com/inward/record.url?scp=0032019190&partnerID=8YFLogxK
U2 - 10.1016/S0038-1101(97)00204-9
DO - 10.1016/S0038-1101(97)00204-9
M3 - Article
AN - SCOPUS:0032019190
VL - 42
SP - 401
EP - 404
JO - Solid-State Electronics
JF - Solid-State Electronics
SN - 0038-1101
IS - 3
ER -