In this paper, a simple and low temperature fabrication process, slow spin rate coating and dry etching, is proposed to construct the CNT-interconnects for future VLSI interconnect applications. Two sets of CNT-interconnects named width and length varying interconnects were fabricated to investigate the characterization of size dependent conductivity of CNT-interconnects. Not only the amount of the CNT solution spin-coated for forming the CNT networks but also the area of CNT-interconnect regime would affect the conductance, variation, and conductive probability of CNT-interconnects. The yield of working CNT-interconnects does not show direct relation with the conductive probability or the amount of the CNT solution for CNT network formation. Based on the percolation theory, we characterize the average conductance of size-varying CNT-interconnects by three regions: percolation region, power region and linear region. In addition, as the density within a specified CNT-interconnect regime accumulates, the conductive behavior would be eventually characterized as a conventional resistor.