Characteristics of gate-all-around junctionless polysilicon nanowire transistors with twin 20-nm gates

Tung Yu Liu, Fu-Ming Pan, Jeng-Tzong Sheu*

*Corresponding author for this work

Research output: Contribution to journalArticle

10 Scopus citations

Abstract

A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high Ion Ioff current ratio of 7 × 10-8 (VG = 4 V and VD = 1 V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.

Original languageEnglish
Article number7118129
Pages (from-to)405-409
Number of pages5
JournalIEEE Journal of the Electron Devices Society
Volume3
Issue number5
DOIs
StatePublished - 1 Sep 2015

Keywords

  • Gate-all-around (GAA)
  • junctionless (JL)
  • nanowire (NW)
  • poly-Si
  • sidewall spacer
  • transistor

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