Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate

Ya-Chi Cheng; Hung Bin Chen; Jun-Ji Su; Chi-Shen Shao; Vasanthan Thirunavukkarasu; Chun-Yen Chang; Yung-Chun Wu

doi:10.1109/LED.2014.2379673

Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate

Ya-Chi Cheng, Hung Bin Chen, Jun-Ji Su, Chi-Shen Shao, Vasanthan Thirunavukkarasu, Chun-Yen Chang, Yung-Chun Wu

International College of Semiconductor Technology

Research output: Contribution to journal › Article

5 Scopus citations

Abstract

This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high I-ON/I-OFF current ratio (>10(7)), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness (T-ch) of 24 nm is 50 times smaller than conventional JL-TFT with T-ch = 12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness.

Original language	English
Pages (from-to)	159-161
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	36
Issue number	2
DOIs	https://doi.org/10.1109/LED.2014.2379673
State	Published - Feb 2015

Keywords

Junctionless (JL); thin-film transistor (TFT); omega-gate; nanowires (NWs)

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Cheng, Y-C., Chen, H. B., Su, J-J., Shao, C-S., Thirunavukkarasu, V., Chang, C-Y., & Wu, Y-C. (2015). Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate. IEEE Electron Device Letters, 36(2), 159-161. https://doi.org/10.1109/LED.2014.2379673

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title = "Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate",

abstract = "This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high I-ON/I-OFF current ratio (>10(7)), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness (T-ch) of 24 nm is 50 times smaller than conventional JL-TFT with T-ch = 12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness.",

keywords = "Junctionless (JL); thin-film transistor (TFT); omega-gate; nanowires (NWs)",

author = "Ya-Chi Cheng and Chen, {Hung Bin} and Jun-Ji Su and Chi-Shen Shao and Vasanthan Thirunavukkarasu and Chun-Yen Chang and Yung-Chun Wu",

year = "2015",

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doi = "10.1109/LED.2014.2379673",

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T1 - Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate

AU - Cheng, Ya-Chi

AU - Chen, Hung Bin

AU - Su, Jun-Ji

AU - Shao, Chi-Shen

AU - Thirunavukkarasu, Vasanthan

AU - Chang, Chun-Yen

AU - Wu, Yung-Chun

PY - 2015/2

Y1 - 2015/2

N2 - This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high I-ON/I-OFF current ratio (>10(7)), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness (T-ch) of 24 nm is 50 times smaller than conventional JL-TFT with T-ch = 12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness.

AB - This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high I-ON/I-OFF current ratio (>10(7)), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness (T-ch) of 24 nm is 50 times smaller than conventional JL-TFT with T-ch = 12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness.

KW - Junctionless (JL); thin-film transistor (TFT); omega-gate; nanowires (NWs)

U2 - 10.1109/LED.2014.2379673

DO - 10.1109/LED.2014.2379673

M3 - Article

VL - 36

SP - 159

EP - 161

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 2

ER -