Abstract
This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high I-ON/I-OFF current ratio (>10(7)), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness (T-ch) of 24 nm is 50 times smaller than conventional JL-TFT with T-ch = 12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness.
Original language | English |
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Pages (from-to) | 159-161 |
Number of pages | 4 |
Journal | IEEE Electron Device Letters |
Volume | 36 |
Issue number | 2 |
DOIs | |
State | Published - Feb 2015 |
Keywords
- Junctionless (JL); thin-film transistor (TFT); omega-gate; nanowires (NWs)