Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate

Ya-Chi Cheng, Hung Bin Chen, Jun-Ji Su, Chi-Shen Shao, Vasanthan Thirunavukkarasu, Chun-Yen Chang, Yung-Chun Wu

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Abstract

This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high I-ON/I-OFF current ratio (>10(7)), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness (T-ch) of 24 nm is 50 times smaller than conventional JL-TFT with T-ch = 12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness.
Original languageEnglish
Pages (from-to)159-161
Number of pages4
JournalIEEE Electron Device Letters
Volume36
Issue number2
DOIs
StatePublished - Feb 2015

Keywords

  • Junctionless (JL); thin-film transistor (TFT); omega-gate; nanowires (NWs)

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    Cheng, Y-C., Chen, H. B., Su, J-J., Shao, C-S., Thirunavukkarasu, V., Chang, C-Y., & Wu, Y-C. (2015). Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate. IEEE Electron Device Letters, 36(2), 159-161. https://doi.org/10.1109/LED.2014.2379673