Characteristic optimization of single- and double-gate tunneling field effect transistors

Kuo Fu Lee*, Yiming Li, Chun Yen Yiu, Zhong Cheng Su, I. Shiu Lo, Hui Wen Cheng, Ming Hung Han, Thet Thet Khaing

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Optimal single- and double-gate tunneling field-effect transistor (TFET) with a structure of p++ source, intrinsic channel and n+ drain region are explored. Two-dimensional device simulation is adopted to assess device characteristic influenced by the source doping, the channel doping and the thickness of junction overlap between the source and gate. The result of this study shows that the source doping and junction overlap significantly affect the drain current (ID). Then, we compare the single- and double-gate TFETs with the optimized parameters, where the junction overlap is 6 nm, the source doping is 1022 cm3, and the intrinsic channel doping. For the explored double-gate TFET, a steeper subthreshold slope (SS) of 32 mV/dec and a higher on/off current ratio (Ion/Ioff) of 5×10 9 are obtained, compared with the single-gate device.

Original languageEnglish
Title of host publicationNanotechnology 2010
Subtitle of host publicationElectronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010
Pages65-68
Number of pages4
StatePublished - 2010
EventNanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010 - Anaheim, CA, United States
Duration: 21 Jun 201024 Jun 2010

Publication series

NameNanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010
Volume2

Conference

ConferenceNanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010
CountryUnited States
CityAnaheim, CA
Period21/06/1024/06/10

Keywords

  • DC characteristic
  • Device simulation
  • Field Effect Transistor
  • On/off state current ratio
  • Optimal parameters
  • Subthreshold slop
  • Tunneling

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  • Cite this

    Lee, K. F., Li, Y., Yiu, C. Y., Su, Z. C., Lo, I. S., Cheng, H. W., Han, M. H., & Khaing, T. T. (2010). Characteristic optimization of single- and double-gate tunneling field effect transistors. In Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010 (pp. 65-68). (Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010; Vol. 2).