Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET

Clement Wann*, Fariborz Assaderaghi, Robert Dennard, Chen-Ming Hu, Ghavam Shahidi, Yuan Taur

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

32 Scopus citations

Abstract

Device design of DTMOS and its parasitic components are discussed. The benefits of operating this device are described. It is shown that DTMOS improves circuit speed when the output capacitance is dominated by wiring capacitance. Vertical doping engineering further improves ΔV t, I dsat, and gate delay. For output capacitance dominated by device capacitance such as in a unloaded ring oscillator, local channel doping should be used to reduce C bs and C bd, whose impact on gate delay can be less in some cases of pass-gate logic. Improved ΔV t can also reduce voltage level loss in pass-gate logic. DTMOS can be a general-purpose, low-power, high performance device for V dd less than 0.6V. 2X improvement in device speed can be obtained with well-designed device doping profiles when wiring capacitance dominates.

Original languageEnglish
Pages (from-to)113-116
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1 Dec 1996
EventProceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: 8 Dec 199611 Dec 1996

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