Device design of DTMOS and its parasitic components are discussed. The benefits of operating this device are described. It is shown that DTMOS improves circuit speed when the output capacitance is dominated by wiring capacitance. Vertical doping engineering further improves ΔV t, I dsat, and gate delay. For output capacitance dominated by device capacitance such as in a unloaded ring oscillator, local channel doping should be used to reduce C bs and C bd, whose impact on gate delay can be less in some cases of pass-gate logic. Improved ΔV t can also reduce voltage level loss in pass-gate logic. DTMOS can be a general-purpose, low-power, high performance device for V dd less than 0.6V. 2X improvement in device speed can be obtained with well-designed device doping profiles when wiring capacitance dominates.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1 Dec 1996|
|Event||Proceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA|
Duration: 8 Dec 1996 → 11 Dec 1996