Challenges to Partial Switching of Hf0.8Zr0.2O2Gated Ferroelectric FET for Multilevel/Analog or Low-Voltage Memory Operation

Korok Chatterjee*, Sangwan Kim, Golnaz Karbasian, Daewoong Kwon, Ava J. Tan, Ajay K. Yadav, Claudy R. Serrao, Chenming Hu, Sayeef Salahuddin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

The ability to partially switch an FeFET could enable their use as an embedded low-voltage memory and as analog weight storage in artificial neural networks (ANNs). We report on memory characterization of FeFETs gated with 5.5-nm Hf0.8Zr0.2O2, fabricated on fully depleted silicon-on-insulator using a self-aligned, gate last process. We find that for a single device, excellent elevated temperature retention, program/erase endurance, and read endurance are obtained;however, there is significantdevice to device variability in the response of the ferroelectric to a partially switching program pulse, which may require the use of feedback in programming.

Original languageEnglish
Article number8777131
Pages (from-to)1423-1426
Number of pages4
JournalIEEE Electron Device Letters
Volume40
Issue number9
DOIs
StatePublished - Sep 2019

Keywords

  • Artificial intelligence
  • Deep learning
  • Ferroelectric
  • Gate last
  • Hafnium zirconium oxide
  • Memory
  • Neuromorphic computing
  • Silicon-on-insulator

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