Challenges for future semiconductor manufacturing

Hiroshi Iwai*, Kuniyuki Kakushima, Hei Wong

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

20 Scopus citations

Abstract

The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.

Original languageEnglish
Pages (from-to)43-81
Number of pages39
JournalInternational Journal of High Speed Electronics and Systems
Volume16
Issue number1
DOIs
StatePublished - Mar 2006

Keywords

  • CMOS technology
  • Device downsizing
  • Semiconductor manufacturing

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