Challenges and designs of TFET for digital applications

Ming Long Fan, Yin Nien Chen, Pin Su*, Ching Te Chuang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Scopus citations

Abstract

This chapter reviews the challenges and designs of digital TFET circuits. Several fundamental features of TFET such as unidirectional conduction, delayed saturation, and enhanced Miller capacitance are described with emphasis on their impacts on the functionality and robustness of logic and SRAM circuits. For TFET logic circuits, structural innovations and device design are demonstrated to facilitate compact circuit design and performance improvement. For SRAM, the advantages of hybrid TFET-MOSFET 8T SRAM cell in stability and efficiency of WRITE-assisted circuit to enhance performance are addressed. Moreover, the variability and backgate bias technique for TFET digital circuit design are highlighted.

Original languageEnglish
Title of host publicationTunneling Field Effect Transistor Technology
PublisherSpringer International Publishing
Pages89-110
Number of pages22
ISBN (Electronic)9783319316536
ISBN (Print)9783319316512
DOIs
StatePublished - 1 Jan 2016

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    Fan, M. L., Chen, Y. N., Su, P., & Chuang, C. T. (2016). Challenges and designs of TFET for digital applications. In Tunneling Field Effect Transistor Technology (pp. 89-110). Springer International Publishing. https://doi.org/10.1007/978-3-319-31653-6_4