CDM ESD protection in CMOS integrated circuits

Ming-Dou Ker*, Yuan Wen Hsiao

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

The impacts of eharged-device-model (CDM) electrostatic discharge (ESD) events on integrated circuit (IC) products are presented in this paper. The mechanism of chip-level CDM ESD event is introduced with some case studies on CDM ESD damages. Besides the chip-level CDM ESD event, the board-level CDM ESD event, which had been reported to cause damages in many customer-returned ICs, is also investigated in this work. The chip-level and board-level CDM ESD levels of several test devices and test circuits fabricated in CMOS processes are characterized and compared. The experimental results have shown that the board-level CDM ESD level of the test circuit is much lower than the chip-level CDM ESD level, which indicates that the board-level CDM ESD test is more critical than the chip-level CDM ESD test in the field applications. In addition, failure analysis reveals that the failure on the test circuit under board-level CDM ESD test is much severer than that under chip-level CDM ESD test.

Original languageEnglish
Title of host publicationProceedings of the Argentine School of Micro-Nanoelectronics, Technology and Applications 2008, EAMTA
Pages61-66
Number of pages6
StatePublished - 24 Nov 2008
EventArgentine School of Micro-Nanoelectronics, Technology and Applications 2008, EAMTA - Buenos Aires, Argentina
Duration: 18 Sep 200819 Sep 2008

Publication series

NameProceedings of the Argentine School of Micro-Nanoelectronics, Technology and Applications 2008, EAMTA

Conference

ConferenceArgentine School of Micro-Nanoelectronics, Technology and Applications 2008, EAMTA
CountryArgentina
CityBuenos Aires
Period18/09/0819/09/08

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