The lateral SCR devices used in CMOS on-chip ESD protection circuits are reviewed. Such SCR devices had been found to be accidentally triggered by noise pulses when the ICs are operated in the application systems. A cascoded design is therefore proposed to safety apply the LVTSCR devices for whole-chip ESD protection in CMOS ICs without causing unexpected operation errors or latchup danger. The temperature dependence on the holding voltage of the cascoded LVTSCRs has been investigated in detail. From the experimental verification, the cascoded LVTSCRs can be fully turned on within a time below 20 ns. The ESD robustness per layout area of the three-cascoded LVTSCRs can be 0.83 V/μm2 in a 0.35-μm silicide CMOS process without using the extra silicide-blocking and ESD-implant masks, whereas the ESD robustness of the gate-grounded NMOS is only 0.25 V/μm2. Such cascoded LVTSCRs with a tunable holding voltage greater than VDD can provide CMOS ICs with effective component-level ESD protection but without causing catchup danger if it is accidentally triggered by the system-level overshooting or undershooting noise pulses.