Capacitorless DRAM cell on SOI substrate

Hsing Jen Wann*, Chen-Ming Hu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

61 Scopus citations

Abstract

We propose a capacitorless DRAM (CDRAM) cell on SOI substrate with large READ current (>100μA/μm), small cell size, and simple fabrication process. PISCES simulations are used to analyze the memory cell operations. The CDRAM cell size is that of a transistor, which makes it very attractive for high density memory applications. Since the fabrication process of CDRAM is compatible with that of the general-purpose SOI CMOS and complementary BiCMOS process, CDRAM can also be used for integrated on-chip memory and is an interesting candidate as the technology driver of SOI VLSI.

Original languageEnglish
Title of host publicationTechnical Digest - International Electron Devices Meeting
Editors Anon
PublisherPubl by IEEE
Pages635-638
Number of pages4
ISBN (Print)0780314506
DOIs
StatePublished - 1 Dec 1993
EventProceedings of the 1993 IEEE International Electron Devices Meeting - Washington, DC, USA
Duration: 5 Dec 19938 Dec 1993

Publication series

NameTechnical Digest - International Electron Devices Meeting
ISSN (Print)0163-1918

Conference

ConferenceProceedings of the 1993 IEEE International Electron Devices Meeting
CityWashington, DC, USA
Period5/12/938/12/93

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  • Cite this

    Wann, H. J., & Hu, C-M. (1993). Capacitorless DRAM cell on SOI substrate. In Anon (Ed.), Technical Digest - International Electron Devices Meeting (pp. 635-638). (Technical Digest - International Electron Devices Meeting). Publ by IEEE. https://doi.org/10.1109/IEDM.1993.347280