Capacitorless DRAM cell on SOI substrate

Hsing Jen Wann; Chen-Ming Hu

doi:10.1109/IEDM.1993.347280

Capacitorless DRAM cell on SOI substrate

Hsing Jen Wann^*, Chen-Ming Hu

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

61 Scopus citations

Abstract

We propose a capacitorless DRAM (CDRAM) cell on SOI substrate with large READ current (>100μA/μm), small cell size, and simple fabrication process. PISCES simulations are used to analyze the memory cell operations. The CDRAM cell size is that of a transistor, which makes it very attractive for high density memory applications. Since the fabrication process of CDRAM is compatible with that of the general-purpose SOI CMOS and complementary BiCMOS process, CDRAM can also be used for integrated on-chip memory and is an interesting candidate as the technology driver of SOI VLSI.

Original language	English
Title of host publication	Technical Digest - International Electron Devices Meeting
Editors	Anon
Publisher	Publ by IEEE
Pages	635-638
Number of pages	4
ISBN (Print)	0780314506
DOIs	https://doi.org/10.1109/IEDM.1993.347280
State	Published - 1 Dec 1993
Event	Proceedings of the 1993 IEEE International Electron Devices Meeting - Washington, DC, USA Duration: 5 Dec 1993 → 8 Dec 1993

Publication series

Name	Technical Digest - International Electron Devices Meeting
ISSN (Print)	0163-1918

Conference

Conference	Proceedings of the 1993 IEEE International Electron Devices Meeting
City	Washington, DC, USA
Period	5/12/93 → 8/12/93

Access to Document

10.1109/IEDM.1993.347280

Link to publication in Scopus

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Cite this

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abstract = "We propose a capacitorless DRAM (CDRAM) cell on SOI substrate with large READ current (>100μA/μm), small cell size, and simple fabrication process. PISCES simulations are used to analyze the memory cell operations. The CDRAM cell size is that of a transistor, which makes it very attractive for high density memory applications. Since the fabrication process of CDRAM is compatible with that of the general-purpose SOI CMOS and complementary BiCMOS process, CDRAM can also be used for integrated on-chip memory and is an interesting candidate as the technology driver of SOI VLSI.",

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AB - We propose a capacitorless DRAM (CDRAM) cell on SOI substrate with large READ current (>100μA/μm), small cell size, and simple fabrication process. PISCES simulations are used to analyze the memory cell operations. The CDRAM cell size is that of a transistor, which makes it very attractive for high density memory applications. Since the fabrication process of CDRAM is compatible with that of the general-purpose SOI CMOS and complementary BiCMOS process, CDRAM can also be used for integrated on-chip memory and is an interesting candidate as the technology driver of SOI VLSI.

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