Capacitance-voltage behaviors of the LTPS TFTs before and after DC stress explained by the slicing model

Yan Fu Kuo*, Shih Che Huang, Yu Te Chao, Ya-Hsiang Tai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The proposed analytical circuit based on the slicing model further explains the behavior of the gate-to-source capacitance CGS and gate-to-drain capacitance CGD curves of the LTPS TFT at different measuring frequencies. The degradation mechanisms and damaged locations can be identified according to the frequency responses of the CGS and CGD curves.

Original languageEnglish
Title of host publicationIDMC 2007 - International Display Manufacturing Conference and FPD Expo - Proceedings
Pages523-525
Number of pages3
StatePublished - 1 Dec 2007
EventInternational Display Manufacturing Conference and Exhibition, IDMC 2007 - Taipei, Taiwan
Duration: 3 Jul 20076 Jul 2007

Publication series

NameIDMC 2007 - International Display Manufacturing Conference and FPD Expo - Proceedings

Conference

ConferenceInternational Display Manufacturing Conference and Exhibition, IDMC 2007
CountryTaiwan
CityTaipei
Period3/07/076/07/07

Keywords

  • Capacitance-voltage
  • DC stress degradation
  • Poly-Si TFTs
  • Slicing model

Fingerprint Dive into the research topics of 'Capacitance-voltage behaviors of the LTPS TFTs before and after DC stress explained by the slicing model'. Together they form a unique fingerprint.

Cite this