CAPACITANCE MEASUREMENT TECHNIQUE IN HIGH DENSITY MOS STRUCTURES.

Hiroshi Iwai*, Susumu Kohyama

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

9 Scopus citations

Abstract

A precise capacitance measurement technique is described. This technique is based on a principle of capacitively divided ac voltage measurement. In test devices, reference and test capacitors are connected in series, and intermediate node signal is monitored by on chip linear sense amplifier. Utilizing the technique, various capacitances were measured, and quantitative compared with a two dimensional numerical analysis. The results indicate that the technique is practical and accurate for evaluating capacitive elements in VLSI's.

Original languageEnglish
Pages (from-to)235-238
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1980
EventTech Dig Int Electron Devices Meet - Washington, DC, USA
Duration: 8 Dec 198010 Dec 1980

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