Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs

Hsien Kai Kuo, Ta Kan Yen, Bo-Cheng Lai, Jing Yang Jou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

On-chip shared cache is effective to alleviate the memory bottleneck in modern many-core systems, such as GPGPUs. However, when scheduling numerous concurrent threads on a GPGPU, a cache capacity agnostic scheduling scheme could lead to severe cache contention among threads and thus significant performance degradation. Moreover, the diverse working sets in irregular applications make the cache contention issue an even more serious problem. As a result, taking cache capacity into account has become a critical scheduling issue of GPGPUs. This paper formulates a Cache Capacity Aware Thread Scheduling Problem to capture the impact of cache capacity as well as different architectural considerations. With a proof to be NP-hard, this paper has proposed two algorithms to perform the cache capacity aware thread scheduling. The simulation results on Nvidia's Fermi configuration have shown that the proposed scheduling scheme can effectively avoid cache contention, and achieve an average of 44.7% cache miss reduction and 28.5% runtime enhancement. The paper also shows the runtime can be enhanced up to 62.5% for more complex applications.

Original languageEnglish
Title of host publication2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
Pages338-343
Number of pages6
DOIs
StatePublished - 20 May 2013
Event2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 - Yokohama, Japan
Duration: 22 Jan 201325 Jan 2013

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
CountryJapan
CityYokohama
Period22/01/1325/01/13

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  • Cite this

    Kuo, H. K., Yen, T. K., Lai, B-C., & Jou, J. Y. (2013). Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs. In 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 (pp. 338-343). [6509618] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2013.6509618