Bulk FinFET With Low-κ Spacers for Continued Scaling

Angada B. Sachid, Min Cheng Chen, Chen-Ming Hu

Research output: Contribution to journalArticlepeer-review

17 Scopus citations


We fabricate n-channel silicon bulk FinFET with silicon nitride (Si3N4) high-κ, silicon nitride/silicon dioxide dual-κ, and silicon dioxide (SiO2) low-κ spacers, and compare their performance using measurements and TCAD simulations. While all the three devices show similar dc performance, the ac and transient performance of low-κ spacer FinFET is better due to lower parasitic capacitance (Cpar). We show that Cpar in SiO2 spacer FinFET is about half of that with Si3N4 spacer. When the gate length is scaled, the contribution of Cpar compared with the intrinsic capacitance (Cox) increases. For FinFET with Si3N4 spacers, Cpar/Cox increases from 36% at 30-nm gate length to 105% when the gate length is scaled to 10 nm, while for FinFET with SiO2 spacers, the ratio changes from 19% to 55% making the latter more suitable for scaling. For SiO2 spacer FinFET, inverter delay is about 13% and 25% lower than Si3N4 spacer FinFET for gate lengths of 30 and 10 nm, respectively.

Original languageEnglish
Article number7859461
Pages (from-to)1861-1864
Number of pages4
JournalIEEE Transactions on Electron Devices
Issue number4
StatePublished - 1 Apr 2017


  • Dual-κ spacer
  • FinFET
  • High-κ spacer
  • Low-κ spacer
  • Nanowire
  • Parasitic capacitance

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