Built-in jitter measurement methodology for spread-spectrum clock generators

Jenchien Hsu*, Maohsuan Chou, Chau-Chin Su

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

In this paper, a built-in-self-test methodology for measuring frequency deviation and jitter of spread-spectrum clock generators is presented. It utilizes a phase detector to detect the clock phase of spread spectrum clock (SSC) and then measure the jitter by filtering out the low frequency component of the clock phase. Frequency of spread-spectrum clock can also be obtained by filtering out the high frequency component of the signal. The methodology is analyzed and verified with chip implementation and measurement. As an all digital design, the hardware overhead is very low.

Original languageEnglish
Title of host publication2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Pages67-72
Number of pages6
DOIs
StatePublished - 5 Sep 2008
Event2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu, Taiwan
Duration: 23 Apr 200825 Apr 2008

Publication series

Name2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Conference

Conference2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
CountryTaiwan
CityHsinchu
Period23/04/0825/04/08

Keywords

  • Jitter measurement
  • Spread-spectrum clock
  • Spread-spectrum clock built-in self test

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