This paper presents how to find optimized buffer size for VLSI architectures of full-search block matching algorithms. Starting from the DG (dependency graph) analysis, we focus in the problem of reducing the internal buffer size under minimal I/O bandwidth constraint. As a result, a systematic design procedure for buffer optimization is derived to reduce realization cost.
|Number of pages||10|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97 - Zurich, Switz|
Duration: 14 Jul 1997 → 16 Jul 1997
|Conference||Proceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97|
|Period||14/07/97 → 16/07/97|