Buffer size optimization for full-search block matching algorithms

Yuan Hau Yeh*, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

This paper presents how to find optimized buffer size for VLSI architectures of full-search block matching algorithms. Starting from the DG (dependency graph) analysis, we focus in the problem of reducing the internal buffer size under minimal I/O bandwidth constraint. As a result, a systematic design procedure for buffer optimization is derived to reduce realization cost.

Original languageEnglish
Pages76-85
Number of pages10
DOIs
StatePublished - 1 Jan 1997
EventProceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97 - Zurich, Switz
Duration: 14 Jul 199716 Jul 1997

Conference

ConferenceProceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97
CityZurich, Switz
Period14/07/9716/07/97

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